1. Field of the Invention
The present invention relates to clock signal generators, and more particularly to a clock signal generator in which a non-overlapping property of non-overlapping clock pulses can be ensured throughout a network of clock signal lines existing on an entire semiconductor chip.
2. Prior Art
FIG. 1 shows a conventional logic circuit of an output stage of a clock signal generator. In FIG. 1, the logic circuit is constituted by inverters 4, 5, 8, 9, 10 and 11, and 2-input NOR gates 6 and 7. 2-phase non-overlapping clock pulses P1 and P2 formed in a pre-stage block of the clock signal generator are applied respectively to the inverters 4 and 5 and 2-phase non-overlapping clock pulses T1 and T2 are distributed to a network of clock signal lines throughout the entire semiconductor. Having no essential relevance to the present invention, the pre-stage for generating the clock pulses P1 and P2 is omitted in the drawing.
Next, the operation of the clock signal generator will be described. Assume that the 2-phase non-overlapping clock pulses P1 and P2 have such waveforms as illustrated in FIG. 2A. If the clock pulses are driven so as to be distributed directly on clock signal lines throughout the entire semiconductor chip, the waveforms of the clock pulses are dulled as illustrated in FIG. 2B because of load capacitance of the respective clock signal lines of the clock pulses T1 and T2. Accordingly, it is required to properly design the circuit on the basis of proper estimation of the load capacitance so that the clock pulses do not have any time period where both the clock pulses become "H" at the same time (hereinafter referred to as "overlapping time period") even if the waveforms of the clock pulses T1 and T2 are dulled. However, it is difficult to properly estimate the parasitic capacity in the stage of designing a circuit arrangement, and if a mistake is caused in design an overlapping time period is caused as illustrated in FIG. 2C. In order to cope with such a mistake in design, the circuit of FIG. 1 is so arranged that the clock pulses T1 and T2 are cross-coupled through the 2-input NOR gates 6 and 7 and lines 12 and 13 so as to prevent the clock pulse T2 from becoming "H" when the clock pulse T1 is "H" and to prevent the clock pulse T1 from becoming "H" when the clock pulse T2 is "H". Accordingly, no overlapping time period occurs in the arrangement of FIG. 1 as illustrated in FIG. 2D.
In the clock signal generator of FIG. 1, however, there is such a problem that the load connected to the clock signal lines for the clock pulses T1 and T2 are not always completely capacitive but generally has a resistive component so that the dulling of the waveforms of the clock pulses are different between a position where the clock pulses are generated and another position separated far away from the first mentioned position, and therefore the non-overlapping property cannot be always ensured in the whole chip region by the arrangement of FIG. 1.